FPGA buck-boost – 02/07/2021 – SPI with FPGA

Having some initial luck learning to program in VHDL, it is time to take on the next challenge. Being able to communicate between our FPGA and a micro-controller is essential to more complex systems where I would actually use an FPGA. I am trying to master this with DMA, so I can store and send registers with data stored in FIFO’s. I am reaching limitations in my ability to debug my code, and in my methods for coding on the FPGA. I have a lot to learn, from better control of clocks with PLL to being able to organize my code better. This is my test bench, using LED’s and an oscilloscope to watch the signals.

To help in learning, I am writing with the Altera group at Intel. Hoping to find guidance on this journey at the forum for developers.

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/SPI-slave/m-p/1255467#M19300

After taking some time to get more familiar with Quartus II for development of FPGA boards using VHDL, I learned to troubleshoot code using the Signal Tap II Logic Analyzer built into the IDE. Now, I can watch any of the pins or signals programmed into the Cyclone II FPGA. It allows me to watch the action while the board is plugged in with the USB-Blaster JTAG debugger. I was able to see the SPI communication from the Raspberry Pi and to watch the user side within VHDL.

Also found to write a more hierarchical code that has a top level, and components so I can coordinate between SPI communications coming in and a PWM output with a duty cycle set by the SPI communication. I use the components as written here

SPI_Slave — https://www.digikey.com/eewiki/pages/viewpage.action?pageId=7569477

PWM — https://www.digikey.com/eewiki/pages/viewpage.action?pageId=20939345

So, at this point, I am able to receive a byte from the SPI that corresponds to the duty cycle I would like to set. I pass that number to the PWM and that is output to a pin that I assign, looking at the Oscilloscope